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ultrafast sige voltage comparators ADCMP580/adcmp581/adcmp582 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 ghz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (dj) 200 fs random jitter (rj) ? 2 v to +3 v input range with +5 v/ ? 5 v supplies on-chip terminations at both input pins resistor-programmable hysteresis differential latch control power supply rejection > 70 db applications automatic test equipment (ate) high speed instrumentation pulse spectroscopy medical imaging and diagnostics high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry clock and data signal restoration general description the ADCMP580/adcmp581/adcmp582 are ultrafast voltage comparators fabricated on analog devices proprietary xfcb3 silicon germanium (sige) bipolar process. the ADCMP580 features cml output drivers; the adcmp581 features reduced swing ecl (negative ecl) output drivers; and the adcmp582 features reduced swing pecl (positive ecl) output drivers. all three comparators offer 180 ps propagation delay and 100 ps minimum pulse width for 10 gbps operation with 200 fs random jitter (rj). overdrive and slew rate dispersion are typically less than 15 ps. the 5 v power supplies enable a wide ? 2 v to +3 v input range with logic levels referenced to the cml/necl/pecl outputs. the inputs have 50 on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. functional block diagram v p noninverting input v tp termination v tn termination v n inverting input le input hys q output q output le input 04672-001 ADCMP580/ adcmp581/ adcmp582 cml/ecl/ pecl figure 1. the cml output stage is designed to directly drive 400 mv into 50 transmission lines terminated to ground. the necl output stages are designed to directly drive 400 mv into 50 terminated to ? 2 v. the pecl output stages are designed to directly drive 400 mv into 50 terminated to v cco ? 2 v. high speed latch and programmable hysteresis are also provided. the differential latch input controls are also 50 terminated to an independent v tt pin to interface to either cml or ecl or to pecl logic. the ADCMP580/adcmp581/adcmp582 are available in a 16-lead lfcsp package.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 2 of 16 table of contents specifications ..................................................................................... 3 timing information ......................................................................... 5 absolute maximum ratings ............................................................ 6 thermal considerations .............................................................. 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 typical application circuits .......................................................... 10 application information ................................................................ 11 power/ground layout and bypassing ..................................... 11 adcmp58x family of output stages ..................................... 11 using/disabling the latch feature ........................................... 11 optimizing high speed performance ..................................... 12 comparator propagation delay dispersion ........................... 12 comparator hysteresis .............................................................. 13 minimum input slew rate requirement ................................ 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 7/05revision 0: initial version
ADCMP580/adcmp581/adcmp582 rev. 0 | page 3 of 16 specifications v cci = +5.0 v; v ee = ?5.0 v; v cco = +3.3 v; t a = 25c, unless otherwise noted. table 1. parameter symbol condition min typ max unit dc input characteristics input voltage range v p , v n ?2.0 +3.0 v input differential range ?2.0 +2.0 v input offset voltage v os ?10.0 4 +10.0 mv offset voltage tempco v os /d t 10 v/c input bias current i p , i n open termination 15 30.0 a input bias current tempco i b /d t 50 na/c input offset current 2 5.0 a input resistance 47 to 53 input resistance, differential mode open termination 50 k input resistance, common mode open termination 500 k active gain a v 48 db common-mode rejection cmrr v cm = ?2.0 v to +3.0 v 60 db hysteresis r hys = 1 mv latch enable characteristics latch enable input impedance z in each pin, v tt at ac ground 47 to 53 latch to output delay t ploh , t plol v od = 200 mv 175 ps latch minimum pulse width t pl v od = 200 mv 100 ps ADCMP580 (cml) latch enable input range ?0.8 0 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 200 mv 95 ps latch hold time t h v od = 200 mv ?90 ps adcmp581 (necl) latch enable input range ?1.8 +0.8 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 200 mv 70 ps latch hold time t h v od = 200 mv ?65 ps adcmp582 (pecl) latch enable input range v cco ? 1.8 v cco ? 0.8 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 200 mv 30 ps latch hold time t h v od = 200 mv ?25 ps dc output characteristics ADCMP580 (cml) output impedance z out 50 output voltage high level v oh 50 to gnd ?0.10 0 0.03 v output voltage low level v ol 50 to gnd ?0.50 ?0.40 ?0.35 v output voltage differential 50 to gnd 340 395 450 mv adcmp581 (necl) output voltage high level v oh 50 to ?2 v, t a = 125c ?0.99 ?0.87 ?0.75 v output voltage high level v oh 50 to ?2 v, t a = 25c ?1.06 ?0.94 ?0.82 v output voltage high level v oh 50 to ?2 v, t a = ?55c ?1.11 ?0.99 ?0.87 v output voltage low level v ol 50 to ?2 v, t a = 125c ?1.43 ?1.26 ?1.13 v output voltage low level v ol 50 to ?2 v, t a = 25c ?1.50 ?1.33 ?1.20 v output voltage low level v ol 50 to ?2 v, t a = ?55c ?1.55 ?1.38 ?1.25 v output voltage differential 50 to ?2.0 v 340 395 450 mv
ADCMP580/adcmp581/adcmp582 rev. 0 | page 4 of 16 parameter symbol condition min typ max unit adcmp582 (pecl) vcco = 3.3 v output voltage high level v oh 50 to v cco ? 2 v, t a = 125c v cco ? 0.99 v cco ? 0.87 v cco ? 0.75 v output voltage high level v oh 50 to v cco ? 2 v, t a = 25c v cco ? 1.06 v cco ? 0.94 v cco ? 0.82 v output voltage high level v oh 50 to v cco ? 2 v, t a = ?55c v cco ? 1.11 v cco ? 0.99 v cco ? 0.87 v output voltage low level v ol 50 to v cco ? 2 v, t a = 125c v cco ? 1.43 v cco ? 1.26 v cco ? 1.13 v output voltage low level v ol 50 to v cco ? 2 v, t a = 25c v cco ? 1.50 v cco ? 1.33 v cco ? 1.20 v output voltage low level v ol 50 to v cco ? 2 v, t a = ?55c v cco ? 1.55 v cco ? 1.35 v cco ? 1.25 v output voltage differential 50 to v cco ? 2.0 v 340 395 450 mv ac performance propagation delay t pd v od = 500 mv 180 ps propagation delay tempco t pd /d t 0.25 ps/c prop delay skewrising transition to falling transition v od = 500 mv, 5 v/ns 10 ps overdrive dispersion 50 mv < v od < 1.0 v 10 ps 10 mv < v od < 200m v 15 ps slew rate dispersion 2 v/ns to 10 v/ns 15 ps pulse width dispersion 100 ps to 5 ns 15 ps duty cycle dispersion 5% to 95% 1.0 v/ns, 15 mhz, v cm = 0.0 v 10 ps common-mode dispersion v od = 0.2 v, ?2 v < v cm < 3 v 5 ps/v equivalent input bandwidth 1 bw eq 0.0 v to 400 mv input t r = t f = 25 ps, 20/80 8 ghz toggle rate >50% output swing 12.5 gbps deterministic jitter dj v od = 500 mv, 5 v/ns prbs 31 ? 1 nrz, 5 gbps 15 ps deterministic jitter dj v od = 200 mv, 5 v/ns prbs 31 ? 1 nrz, 10 gbps 25 ps rms random jitter rj v od = 200 mv, 5 v/ns, 1.25 ghz 0.2 ps minimum pulse width pw min t pd < 5 ps 100 ps minimum pulse width pw min t pd < 10 ps 80 ps rise/fall time t r, t f 20/80 37 ps power supply positive supply voltage v cci +4.5 +5.0 +5.5 v negative supply voltage v ee ?5.5 ?5.0 ?4.5 v ADCMP580 (cml) positive supply current i vcci v cci = +5.0 v, 50 to gnd 6 8 ma negative supply current i vee v ee = ?5.0 v, 50 to gnd ?50 ?40 ?34 ma power dissipation p d 50 to gnd 230 260 mw adcmp581 (necl) positive supply current i vcci v cci = +5.0 v, 50 to ?2 v 6 8 ma negative supply current i vee v ee = ?5.0 v, 50 to ?2 v ?35 ?25 ?19 ma power dissipation p d 50 to ?2 v 155 200 mw adcmp582 (pecl) logic supply voltage v cco +2.5 +3.3 +5.0 v input supply current i vcci v cci = +5.0 v, 50 to v cco ? 2 v 6 8 ma output supply current i vcco v cco = +5.0 v, 50 to v cco ? 2 v 44 55 ma negative supply current i vee v ee = ?5.0 v, 50 to v cco ? 2 v ?35 ?25 ?19 ma power dissipation p d 50 to v cco ? 2 v 310 350 mw power supply rejection (v cci ) psr vcci v cci = 5.0 v + 5% ?75 db power supply rejection (v ee ) psr vee v ee = ?5.0 v + 5% ?60 db power supply rejection (v cco ) psr vcco v cco = 3.3 v + 5% (adcmp582) ?75 db 1 equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: bw eq = 0.22/( tr comp 2 C tr in 2 ), where tr in is the 20/80 transition time of a quasi-gaussian input edge applied to the comparator input and tr comp is the effective transition time digitized by the comparator.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 5 of 16 timing information figure 2 shows the ADCMP580/adcmp581/adcmp582 compare and latch timing relationships. table 2 provides the definitions of the terms shown in the figure. 50% 50% v n v os 50% differential input voltage latch enable q output q output latch enable t h t pdl t pdh t ploh t plol t r t f v n v od t s t pl 04672-028 figure 2. comparator timing diagram table 2. timing descriptions mbol timing description t pdh input to output high delay propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. t pdl input to output low delay propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. t ploh latch enable to output high delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. t plol latch enable to output low delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. t h minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. t pl minimum latch enable pulse width minimum time that the latch enable signal must be high to acquire an input signal change. t s minimum setup time minimum time before the negative transiti on of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. t r output rise time amount of time required to transition fr om a low to a high output as measured at the 20% and 80% points. t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points. v n normal input voltage difference between the input voltages v p and v n for output true. v od voltage overdrive difference between the input voltages v p and v n for output false.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 6 of 16 absolute maximum ratings table 3. parameter rating supply voltages positive supply voltage (v cci to gnd) ?0.5 v to +6.0 v negative supply voltage (v ee to gnd) C6.0 v to +0.5 v logic supply voltage (v cco to gnd) ?0.5 v to +6.0 v input voltages input voltage ?3.0 v to +4.0 v differential input voltage ?2 v to +2 v input voltage, latch enable ?2.5 v to +5.5 v hysteresis control pin applied voltage (hys to v ee ) ?5.5 v to +0.5 v maximum input/output current 1 ma output current ADCMP580 (cml) ?25 ma adcmp581 (necl) ?40 ma adcmp582 (pecl) ?40 ma temperature operating temperature, ambient ?40c to +125c operating temperature, junction 125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal considerations the ADCMP580/adcmp581/adcmp582 lfcsp 16-lead package option has a ja (junction-to-ambient thermal resistance) of 70c/w in still air. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 7 of 16 pin configurations a nd function descriptions q le pin 1 indicator 1v tp 2v p 3v n 4v tn 11 q 12 gnd 10 9 gnd 5 v c c i 6 7 l e 8 v t t 1 5 g n d 1 6 v c c i 1 4 h y s 1 3 v e e ADCMP580 top view (not to scale) 04672-002 04672-003 q le pin 1 indicator 1v tp 2v p 3v n 4v tn 11 q 12 gnd 10 9 gnd 5 v c c i 6 7 l e 8 v t t 1 5 g n d 1 6 v c c i 1 4 h y s 1 3 v e e adcmp581 top view (not to scale) 04672-004 q le pin 1 indicator 1v tp 2v p 3v n 4v tn 11 q 12 v cco 10 9v cco 5 v c c i 6 7 l e 8 v t t 1 5 g n d 1 6 v c c i 1 4 h y s 1 3 v e e adcmp582 top view (not to scale) figure 3. ADCMP580 pin configuration figure 4. adcmp581 pin configuration figure 5. adcmp582 pin configuration table 4. pin function descriptions pin no. mnemonic description 1 v tp termination resistor return pin for vp input. 2 v p noninverting analog input. 3 v n inverting analog input. 4 v tn termination resistor return pin for v n input. 5, 16 v cci positive supply voltage. 6 le latch enable input pin, inverting side. in compare mode ( le = low), the output tracks changes at the input of the comparator. in latch mode ( le = high), the output reflects the inp ut state just prior to the comparator being placed into latch mode. le must be driven in complement with le. 7 le latch enable input pin, noninverting side. in comp are mode (le = high), th e output tracks changes at the input of the comparator. in latch mode (le = low), the output reflects the input state just prior to the comparator being placed into latch mode. le must be driven in complement with le . 8 v tt termination return pin for the le/ le input pins. for the ADCMP580 (cml output stage), this pi n should be connected to the gnd ground. for the adcmp581 (ecl output stage), this pin should be connected to the C2 v termination potential. for the adcmp582 (pecl output stage), this pin should be connected to the v cco C 2 v termination potential. 9, 12 gnd/v cco digital ground pin/positive logic power supply terminal. for the ADCMP580/adcmp581, this pin should be connected to the gnd pin. for the adcmp582, this pin should be connected to the positive logic power v cco supply. 10 q inverting output. q is logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided that the comparator is in compare mode. see the le/ le descriptions (pin 6 to pin 7) for more information. 11 q noninverting output. q is logic high if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided that the comparator is in compare mode. see the le/ le descriptions (pin 6 to pin 7) for more information. 13 v ee negative power supply. 14 hys hysteresis control. leave this pin disconnected for zero hysteresis. connect this pin to the vee supply with a suitably sized resistor to add the desired amount of hysteresis. refer to figure 9 for proper sizing of the hys hysteresis control resistor. 15 gnd analog ground. heat sink paddle n/c the metallic back surface of the package is not electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the pack age handle and the substrate of the die. it can also be soldered to the application board if improved th ermal and/or mechanical stability is desired.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 8 of 16 typical performance characteristics v cci = +5.0 v, v ee = ? 5.0 v, v cco = +3.3 v, t a = 25c, unless otherwise noted. 12 0 ?4 4 04672-005 common mode (v) bias current ( a) 10 8 6 4 2 ?2 0 2 vin common-mode bias sweep figure 6. bias current vs. common-mode voltage ?0.8 ?1.5 ?55 145 04672-007 temp ( c) output (v) ?0.9 ?1.0 ?1.1 ?1.2 ?1.3 ?1.4 ?5 45 95 vol vs temp output (necl) voh vs temp output (necl) figure 7. adcmp581 output voltage vs. temperature 80 0 0 600 04672-008 ?ihyst ( a) hysteresis (mv) 70 60 50 40 30 20 10 100 200 300 400 500 figure 8. hysteresis vs. ?ihyst 80 0 0 10k 04672-009 resistor ( ) hysteresis (mv) 70 60 50 40 30 20 10 10 100 1k figure 9. hysteresis vs. r hys control resistor 2.5 1.9 ?55 145 04672-010 temp ( c) output (v) 2.4 2.3 2.2 2.1 2.0 ?5 45 95 voh vs temp output (pecl) vol vs temp output (pecl) figure 10. adcmp582 output voltage vs. temperature 8 0 ?2 4 04672-011 common-mode (v) offset (mv) 7 6 5 4 3 1 2 02 25 c common-mode offset sweep ?55 c common-mode offset sweep 125 c common-mode offset sweep figure 11. a typical vos vs. common- mode voltage
ADCMP580/adcmp581/adcmp582 rev. 0 | page 9 of 16 5 ?5 ?2 3 04672-031 v cm (v) t pd error (ps) 4 3 2 1 0 ?1 ?2 ?3 ?4 ? 1012 lot2 char1 rise lot2 char1 fall lot3 char1 rise lot3 char1 fall figure 12. ADCMP580 prop delay vs. common-mode voltage 04672-029 m1 m1 figure 13. ADCMP580 eye diagram at 7.5 gbps 18 0 0 250 04672-032 overdrive (mv) dispersion (ps) 16 14 12 10 8 6 4 2 50 100 150 200 od dispersion rise od dispersion fall figure 14. dispersion vs. overdrive 45 25 ?55 125 04672-033 temperature ( c) t r /t f (ps) 43 41 39 37 35 33 31 27 29 ?35 ?15 5 25 45 65 85 105 qbarrise qrise qbarfall qfall figure 15. adcmp581 t r /t f vs. temperature 04672-030 m1 500mv 500mv m1 20ps/div figure 16. adcmp582 eye diagram at 2.5 gbps
ADCMP580/adcmp581/adcmp582 rev. 0 | page 10 of 16 typical application circuits q ADCMP580 q v in v p v tp v tn v n latch inputs 04672-020 50 50 gnd figure 17. zero-crossing detector with cml outputs q adcmp581 q v p v n v tt v p v tp v tn v n latch inputs 04672-021 50 50 figure 18. lvds to a 50 back-terminated (rs) ecl receiver hys v ee 50 50 04672-026 ADCMP580 0 to 5k figure 19. adding hysteres is using the hys control 50 50 + ? q q v in v th latch inputs 04672-022 gnd ADCMP580 figure 20. comparator with ?2 to +3 v input range v p v n v ee 04672-025 ADCMP580 50 1.5k 50 cml figure 21. disabling the latc h feature on the ADCMP580 v p v n 04672-023 adcmp581 v tt v ee 50 50 450 rsecl figure 22. disabling the latc h feature on the adcmp581 v p v n v tt 04672-027 adcmp582 50 1k 50 rspecl figure 23. disabling the latc h feature on the adcmp582
ADCMP580/adcmp581/adcmp582 rev. 0 | page 11 of 16 application information power/ground layout and bypassing the adcmp58x family of comparators is designed for very high speed applications. consequently, high speed design techniques must be used to achieve the specified performance. it is critically important to use low impedance supply planes, particularly for the negative supply (v ee ), the output supply plane (v cco ), and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. provid- ing the lowest inductance return path for the switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. a 1 f electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. in addition, multiple high quality 0.1 f bypass capacitors should be placed as close as possible to each of the v ee , v cci , and v cco supply pins and should be connected to the gnd plane with redundant vias. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should be strictly avoided to maximize the effectiveness of the bypass at high frequencies. adcmp58x family of output stages specified propagation delay dispersion performance is achieved by using proper transmission line terminations. the outputs of the ADCMP580 family comparators are designed to directly drive 400 mv into 50 cable or microstrip/stripline transmis- sion lines terminated with 50 referenced to the proper return. the cml output stage is shown in the simplified schematic diagram in figure 24 . each output is back-terminated with 50 for best transmission line matching. the outputs of the adcmp581/adcmp582 are illustrated in figure 25 ; they should be terminated to ?2 v for ecl outputs of adcmp581 and v cco ? 2 v for pecl outputs of adcmp582. as an alter- native, thevenin equivalent termination networks may also be used. if these high speed signals must be routed more than a centimeter, then either microstrip or stripline techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width-dependent propagation delay dispersion. q 16ma 50 50 q 04672-014 gnd v ee figure 24. simplified schematic diagram of the ADCMP580 cml output stage 04672-015 gnd / vcco v ee q q figure 25. simplified schematic diagram of the adcmp581/adcmp582 ecl/pecl output stage using/disabling the latch feature the latch inputs (le/ le ) are active low for latch mode and are internally terminated with 50 resistors to the v tt pin. when using the ADCMP580, v tt should be connected to ground. when using the adcmp581, v tt should be connected to ?2 v. when using the adcmp582, v tt should be connected externally to v cco ? 2 v, preferably with its own low inductance plane. when using the ADCMP580/adcmp582, the latch function can be disabled by connecting the le pin to v ee with an external pull-down resistor and leaving the le pin discon- nected. to prevent excessive power dissipation, the resistor should be 1.5 k for the ADCMP580 and 1 k for the adcmp582. when using the adcmp581 comparators, the latch can be disabled by connecting the le pin to gnd with an external 450 resistor and leaving the le pin disconnected. the idea is to create an approximate 0.5 v offset using the internal resistor as half of the voltage divider. the v tt pin should be connected as recommended.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 12 of 16 optimizing high speed performance as with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and can cause oscillation. discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance. for applications in a 50 environment, input and output matching have a significant impact on data-dependent (or deterministic) jitter (dj) and pulse width dispersion performance. the adcmp58x family of comparators provides internal 50 termination resistors for both v p and v n inputs. the return side for each termination is pinned out separately with the v tp and v tn pins, respectively. if a 50 termination is desired at one or both of the v p /v n inputs, the v tp and v tn pins can be connected (or disconnected) to (from) the desired termination potential as appropriate. the termination potential should be carefully bypassed using ceramic capacitors as dis- cussed previously to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. if a 50 termination is not desired, either one or both of the v tp /v tn termination pins can be left disconnected. in this case, the open pins should be left floating with no external pull downs or bypassing capacitors. for applications that require high speed operation but do not have on-chip 50 termination resistors, some reflections should be expected, because the comparator inputs can no longer provide matched impedance to the input trace leading up to the device. it then becomes important to back-match the drive source impedance to the input transmission path leading to the input to minimize multiple reflections. for applications in which the comparator is less than 1 cm from the driving signal source, the source impedance should be minimized. high source impedance in combination with parasitic input capaci- tance of the comparator could cause undesirable degradation in bandwidth at the input, thus degrading the overall response. it is therefore recommended that the drive source impedance should be no more than 50 for best high speed performance. comparator propagation delay dispersion the adcmp58x family of comparators has been specifically designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mv to 500 mv. propagation delay dispersion is a change in propagation delays, which results from a change in the degree of overdrive or slew rate (how far or fast the input signal exceeds the switching threshold). the overall result is a higher degree of timing accuracy. propagation delay dispersion is a specification that becomes important in critical timing applications, such as data commu- nication, automatic test and measurement, instrumentation, and event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in the overall propagation delay as the input overdrive conditions are changed (see figure 26 and figure 27 ). for the adcmp58x family of comparators, disper- sion is typically <25 ps, as the overdrive varies from 5 mv to 500 mv, and the input slew rate varies from 1 v/ns to 10 v/ns. this specification applies for both positive and negative signals, because the adcmp58x family of comparators has almost equal delays for positive- and negative-going inputs. q/q output input voltage 500mv overdrive 5mv overdrive dispersion v n v os 04672-016 figure 26. propagation delayoverdrive dispersion q/q output input voltage 10v/ns 1v/ns dispersion v n v os 04672-017 figure 27. propagation delayslew rate dispersion
ADCMP580/adcmp581/adcmp582 rev. 0 | page 13 of 16 comparator hysteresis adding hysteresis to a comparator is often desirable in a noisy environment or when the differential inputs are very small or slow moving. the transfer function for a comparator with hysteresis is shown in figure 28 . if the input voltage approaches the threshold from the negative direction, the comparator switches from a low to a high when the input crosses +v h /2. the new switching threshold becomes ?v h /2. the comparator remains in the high state until the threshold ?v h /2 is crossed from the positive direction. in this manner, noise centered on 0 v input does not cause the comparator to switch states unless it exceeds the region bounded by v h /2. the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. a limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance and can even reduce overall stability in some cases. output input 0v 0 1 +v h 2 ? v h 2 04672-018 f igure 28. comparator hysteresis transfer function the adcmp58x family of comparators offers a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. by connecting an external pull-down resistor from the hys pin to v ee , a variable amount of hysteresis can be applied. leaving the hys pin disconnected disables the feature, and hysteresis is then less than 1 mv, as specified. the maximum range of hysteresis that can be applied by using this method is approximately 25 mv. figure 29 illustrates the amount of applied hysteresis as a function of external resistor value. the advantage of applying hysteresis in this manner is improved accuracy, stability, and reduced component count. an external bypass capacitor is not required on the hys pin and it would likely degrade the jitter performance of the device. the hysteresis pin may also be driven by a current source. it is biased approximately 400 mv above v ee and has an internal series resistance of approximately 600 . 80 0 0 10k 04672-034 resistor ( ) hysteresis (mv) 70 60 50 40 30 20 10 10 100 1k figure 29. comparator hysteresis vs. r hys control resistor minimum input slew rate requirement as with many high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. this oscil- lation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. a minimum slew rate of 50 v/s should ensure clean output transitions from the adcmp58x family of comparators. the slew rate may be too slow for other reasons. the extremely high bandwidth of these devices means that broadband noise can be a significant factor when input slew rates are low. there is 120 v of thermal noise generated over the comparators bandwidth by the two 50 terminations at room temperature. with a slew rate of only 50 v/s, the inputs will be inside this noise band for over 2 ps, rendering the comparators jitter performance of 200 fs irrelevant. raising the slew rate of the input signal and/or reducing the bandwidth over which that resistance is seen at the input can greatly reduce jitter. we do not characterize the devices this way, but simply bypassing a reference input close to the package can reduce jitter 30% in low slew rate applications.
ADCMP580/adcmp581/adcmp582 rev. 0 | page 14 of 16 outline dimensions 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 30. 16-lead lead frame chip scale package [lfcsp_vq] (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADCMP580bcp-wp ?40c to +125c 16-lead lfcsp-vq cp-16-3 go7 ADCMP580bcpCr2 ?40c to +125c 16-lead lfcsp-vq cp-16-3 go7 ADCMP580bcpCrl7 ?40c to +125c 16-lead lfcsp-vq cp-16-3 go7 adcmp581bcp-wp ?40c to +125c 16-lead lfcsp-vq cp-16-3 go9 adcmp581bcpCr2 ?40c to +125c 16-lead lfcsp-vq cp-16-3 go9 adcmp581bcpCrl7 ?40c to +125c 16-lead lfcsp-vq cp-16-3 go9 adcmp582bcp-wp ?40c to +125c 16-lead lfcsp-vq cp-16-3 gob adcmp582bcp-r2 ?40c to +125c 16-lead lfcsp-vq cp-16-3 gob adcmp582bcp-rl7 ?40c to +125c 16-lead lfcsp-vq cp-16-3 gob eval-ADCMP580bcp evaluation board eval-adcmp581bcp evaluation board eval-adcmp582bcp evaluation board
ADCMP580/adcmp581/adcmp582 rev. 0 | page 15 of 16 notes
ADCMP580/adcmp581/adcmp582 preliminary technical data rev. 0 | page 16 of 16 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04672-0-7/05(0)

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